Recent advance in semiconductor manufacturing and design-for-test (DFT) technology has produced very high-quality integrated circuits containing millions of gates. The most popular DFT techniques used to-date in an integrated circuit include scan, memory BIST (built-in self-test), logic BIST, and boundary-scan. See the books written by Abromovici et al. (1990), Nadeau-Dostie (2000), and Crouch (2000). These DFT techniques have made an integrated circuit more testable and yielded lower test costs than using ad hoc functional test techniques. However, it is becoming more and more difficult to guarantee that the integrated circuit, even embedded with DFT circuitries, will function the first time.
Prior-art approaches to prototype debug or diagnosis center on using an ATE (automatic test equipment) or an electronic-beam (E-beam) tester to debug or diagnose physical failures in the integrated circuit. This process is tedious and time-consuming, as it requires collaborative efforts between design engineers and test engineers, and heavily relies on the tester's availability.
While these approaches can eventually identify physical failures in the integrated circuit, it is still highly possible that the chip won't work on an evaluation board or system due to undiscovered timing errors on the ATE or missing functional specification. Consequently, design engineers must embed diagnostics features in the integrated circuit and debug the circuit's functional errors on an evaluation board or system separately. See U.S. Pat. No. 5,488,688 (1996), U.S. Pat. No. 5,491,793 (1996), U.S. Pat. No. 5,544,311 (1996), U.S. Pat. No. 5,724,505 (1998), U.S. Pat. No. 5,828,824 (1998), U.S. Pat. No. 5,828,825 (1998), and U.S. Pat. No. 6,249,893 (2001). This missing link between DFT verification on an ATE and functional verification on an evaluation board or system could potentially miss the chip's time-to-market or time-to-volume window.
Thus, there is a need to provide an improved method and apparatus for debugging or diagnosing DFT and functional errors in an integrated circuit placed on an evaluation board or system using a low-cost DFT debugger. There is also a need to develop such a computer-aided design (CAD) method for automatically synthesizing the design-for-debug (DFD) circuitries in the integrated circuit.